Within the Vertical Orientation (U-Shaped) Racetrack > 자유게시판

• 목록
• 답변
• 글쓰기
• 게시판 리스트 옵션
  • 수정
  • 삭제

Racetrack memory or domain-wall memory (DWM) is an experimental non-unstable memory gadget under improvement at IBM's Almaden Analysis Center by a group led by physicist Stuart Parkin. It is a current matter of active research on the Max Planck Institute of Microstructure Physics in Dr. Parkin's group. In early 2008, a 3-bit model was efficiently demonstrated. If it have been to be developed efficiently, racetrack memory would offer storage density increased than comparable stable-state memory gadgets like flash memory. Racetrack memory uses a spin-coherent electric current to maneuver magnetic domains alongside a nanoscopic permalloy wire about 200 nm throughout and a hundred nm thick. As present is passed via the wire, the domains cross by magnetic learn/write heads positioned near the wire, which alter the domains to record patterns of bits. A racetrack memory device is made up of many such wires and read/write parts. In general operational concept, racetrack memory is much like the earlier bubble Memory Wave Method of the 1960s and 1970s. Delay-line memory, equivalent to mercury delay strains of the 1940s and 1950s, are a still-earlier type of related expertise, as used within the UNIVAC and EDSAC computer systems.

Like bubble memory, racetrack memory uses electrical currents to "push" a sequence of magnetic domains by means of a substrate and previous read/write parts. Improvements in magnetic detection capabilities, primarily based on the development of spintronic magnetoresistive sensors, allow the usage of a lot smaller magnetic domains to supply far larger bit densities. 50 nm. There have been two arrangements thought of for racetrack memory. The best was a series of flat wires arranged in a grid with read and write heads arranged nearby. A extra broadly studied arrangement used U-formed wires arranged vertically over a grid of learn/write heads on an underlying substrate. This may allow the wires to be for much longer without increasing its 2D space, although the need to maneuver particular person domains additional alongside the wires earlier than they attain the learn/write heads ends in slower random entry instances. Both preparations provided about the identical throughput efficiency. The first concern by way of development was sensible; whether or not or not the three dimensional vertical association could be possible to mass-produce.

Projections in 2008 urged that racetrack memory would offer efficiency on the order of 20-32 ns to learn or write a random bit. This compared to about 10,000,000 ns for a tough drive, or 20-30 ns for typical DRAM. The first authors mentioned methods to improve the entry times with using a "reservoir" to about 9.5 ns. Aggregate throughput, with or with out the reservoir, would be on the order of 250-670 Mbit/s for racetrack Memory Wave, in comparison with 12800 Mbit/s for a single DDR3 DRAM, a thousand Mbit/s for prime-efficiency onerous drives, and one thousand to 4000 Mbit/s for flash memory devices. The only present expertise that provided a clear latency benefit over racetrack memory was SRAM, on the order of 0.2 ns, but at the next value. Bigger characteristic dimension "F" of about forty five nm (as of 2011) with a cell area of about 140 F2. Racetrack memory is one amongst a number of emerging applied sciences that intention to change standard memories similar to DRAM and Flash, and potentially provide a common memory system applicable to a large variety of roles.

Other contenders included magnetoresistive random-access memory (MRAM), part-change memory (PCRAM) and ferroelectric RAM (FeRAM). Most of those technologies offer densities just like flash memory, usually worse, and their main benefit is the lack of write-endurance limits like those in flash memory. Subject-MRAM provides wonderful efficiency as high as 3 ns access time, but requires a big 25-40 F² cell measurement. It would see use as an SRAM substitute, however not as a mass storage device. The highest densities from any of these devices is obtainable by PCRAM, with a cell size of about 5.8 F², much like flash memory, in addition to fairly good efficiency around 50 ns. Nevertheless, none of these can come close to competing with racetrack memory in general phrases, particularly density. 4 F², simply exceeding the efficiency-density product of PCM. Usually, memory units retailer one bit in any given location, so they're typically compared in terms of "cell dimension", Memory Wave Method a cell storing one bit.

Cell size itself is given in units of F², the place "F" is the feature dimension design rule, representing normally the metallic line width. Flash and racetrack each store multiple bits per cell, however the comparison can still be made. DRAM has a cell measurement of about 6 F², SRAM is much less dense at one hundred twenty F². NAND flash memory is at present the densest type of non-risky memory in widespread use, with a cell size of about 4.5 F², however storing three bits per cell for an effective size of 1.5 F². NOR flash memory is slightly less dense, at an effective 4.75 F², accounting for 2-bit operation on a 9.5 F² cell size. In the vertical orientation (U-shaped) racetrack, almost 10-20 bits are saved per cell, which itself would have a bodily dimension of not less than about 20 F². A hundred m/s past the learn/write sensor. One limitation of the early experimental units was that the magnetic domains might be pushed solely slowly by way of the wires, requiring present pulses on the orders of microseconds to maneuver them efficiently.