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The second essential timing difference is that fast PWM holds the output high for one cycle longer than the output evaluate register value. 1 cycles when the output compare register is ready to N so an output evaluate register value of 255 is 100% obligation cycle, but an output examine register worth of 0 isn't 0% obligation cycle but 1/256 obligation cycle. This is not like phase-appropriate PWM, where a register worth of 255 is 100% duty cycle and a worth of zero is a 0% duty cycle. How can this be, when a fast PWM worth of 0 yields a responsibility cycle of 1/256 as defined above? The next code fragment units up fast PWM on pins 3 and 11 (Timer 2), utilizing OCR2A as the highest worth for the timer. The next code fragment sets up part-appropriate PWM on pins three and 11 (Timer 2), utilizing OCR2A as the highest worth for the timer

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